MC68HC08AS32 Datasheet, PDF (177/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

FE — Receiver Framing Error Bit
This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE
generates an SCI error CPU interrupt request if the FEIE bit in SCC3 also is set.
Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset
clears the FE bit.
1 = Framing error detected
0 = No framing error detected
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error in
incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3
is also set. Clear the PE bit by reading SCS1 with PE set and then reading the
SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
DELAYED FLAG CLEARING SEQUENCE
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
BYTE 4
BYTE 1
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
Figure 12-12. Flag Clearing Sequence
BYTE 4
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
177