MC68HC08AS32 Datasheet, PDF (73/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

BDRxD
TO PHYSICAL INTERFACE
BDTxD
DLOOP FROM BCR2
LOOPBACK CONTROL
LOOPBACK
MULTIPLEXER
STATE MACHINE
Rx SHIFT REGISTER
Rx SHADOW REGISTER
8
Tx SHIFT REGISTER
Tx SHADOW REGISTER
8
TO CPU INTERFACE AND Rx/Tx BUFFERS
Figure 4-15. BDLC Protocol Handler Outline
4.5.3 Rx and Tx Shadow Registers
Immediately after the Rx shift register has completed shifting in a byte of data, this
data is transferred to the Rx shadow register and RDRF or RXIFR is set (see 4.6.4
BDLC State Vector Register) and an interrupt is generated if the interrupt enable
bit (IE) in BCR1 is set. After the transfer takes place, this new data byte in the Rx
shadow register is available to the CPU interface, and the Rx shift register is ready
to shift in the next byte of data. Data in the Rx shadow register must be retrieved
by the CPU before it is overwritten by new data from the Rx shift register.
Once the Tx shift register has completed its shifting operation for the current byte,
the data byte in the Tx shadow register is loaded into the Tx shift register. After this
transfer takes place, the Tx shadow register is ready to accept new data from the
CPU when TDRE flag in BSVR is set.
4.5.4 Digital Loopback Multiplexer
The digital loopback multiplexer connects RxD to either BDTxD or BDRxD,
depending on the state of the DLOOP bit in the BCR2 register (See 4.6.3 BDLC
Control Register 2).
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
73