MC68HC08AS32 Datasheet, PDF (210/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

14.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started
by a software write to the SPDR ($0012). CPHA has no effect on the delay to the
start of the transmission, but it does affect the initial state of the SCK signal.
When CPHA = 0, the SCK signal remains inactive for the first half of the first SCK
cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line
from its inactive to its active level. The SPI clock rate (selected by SPR1–SPR0)
affects the delay from the write to SPDR and the start of the SPI transmission. (See
Figure 14-8.) The internal SPI clock in the master is a free-running derivative of the
internal MCU clock. It is only enabled when both the SPE and SPMSTR bits
(SPCR) are set to conserve power. SCK edges occur halfway through the low time
of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where
the write to the SPDR will occur relative to the slower SCK. This uncertainty causes
the variation in the initiation delay shown in Figure 14-8. This delay will be no
longer than a single SPI bit time. That is, the maximum delay between the write to
SPDR and the start of the SPI transmission is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles
for DIV128.
14.6 Error Conditions
Two flags signal SPI error conditions:
1. Overflow (OVRFin SPSCR) — Failing to read the SPI data register before
the next byte enters the shift register sets the OVRF bit. The new byte does
not transfer to the receive data register, and the unread byte still can be read
by accessing the SPI data register. OVRF is in the SPI status and control
register.
2. Mode fault error (MODF in SPSCR) — The MODF bit indicates that the
voltage on the slave select pin (SS) is inconsistent with the mode of the SPI.
MODF is in the SPI status and control register.
14.6.1 Overflow Error
The overflow flag (OVRF in SPSCR) becomes set if the SPI receive data register
still has unread data from a previous transmission when the capture strobe of bit 1
of the next transmission occurs. (See Figure 14-5 and Figure 14-7.) If an overflow
occurs, the data being received is not transferred to the receive data register so
that the unread data can still be read. Therefore, an overflow error always indicates
the loss of data.
Data Sheet
210
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor