MC68HC08AS32 Datasheet, PDF (221/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

14.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR, $0010)
• SPI status and control register (SPSCR, $0011)
• SPI data register (SPDR, $0012)
14.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Address: $0010
6
5
4
3
2
1
Read:
Write:
SPRIE
R
SPMSTR CPOL
CPHA SPWOM
SPE
Reset:
0
0
1
0
1
0
0
R
= Reserved
Figure 14-14. SPI Control Register (SPCR)
Bit 0
SPTIE
0
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the SPRF bit.
The SPRF bit is set when a byte transfers from the shift register to the receive
data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode operation.
Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
CPOL — Clock Polarity Bit
This read/write bit determines the logic state of the SPSCK pin between
transmissions. (See Figure 14-5 and Figure 14-7.) To transmit data between
SPI modules, the SPI modules must have identical CPOL bits. Reset clears the
CPOL bit.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
221