MC68HC08AS32 Datasheet, PDF (254/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs.
Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a
logic 0 to it before exiting the break routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
16.2.2.2 Break Address Registers
The break address registers contain the high and low bytes of the desired
breakpoint address. Reset clears the break address registers.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: _{BIT 15}
BIT 13
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
Write:
Reset:
0
0
0
0
0
0
0
0
Figure 16-4. Break Address Register (BRKH)
Address: $FE0D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write: ^{BIT 7}
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reset:
0
0
0
0
0
0
0
0
Figure 16-5. Break Address Register (BRKL)
16.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
16.2.3.1 Wait Mode
If enabled, the break module is active in wait mode. The SIM break stop/wait bit
(SBSW) in the SIM break status register indicates whether wait was exited by a
break interrupt. If so, the user can modify the return address on the stack by
subtracting one from it to re-execute the stop or wait opcode. (See 13.7.1 SIM
Break Status Register.)
16.2.3.2 Stop Mode
The break module is inactive in stop mode. The STOP instruction does not affect
break module register states. A break interrupt will cause an exit from stop mode
and sets the SBSW bit in the SIM break status register.
Data Sheet
254
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor