MC68HC08AS32 Datasheet, PDF (68/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Data Sheet
68
In Huntsinger’s’ variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the symbols
received are defined with no gaps between definitions. For example, the maximum
length of a passive logic 0 is equal to the minimum length of a passive logic 1, and
the maximum length of an active logic 0 is equal to the minimum length of a valid
SOF symbol.
Invalid Passive Bit
See Figure 4-9(1). If the passive-to-active received transition beginning the
next data bit or symbol occurs between the active-to-passive transition
beginning the current data bit (or symbol) and a, the current bit would be invalid.
Valid Passive Logic 0
See Figure 4-9(2). If the passive-to-active received transition beginning the
next data bit (or symbol) occurs between a and b, the current bit would be
considered a logic 0.
Valid Passive Logic 1
See Figure 4-9(3). If the passive-to-active received transition beginning the
next data bit (or symbol) occurs between b and c, the current bit would be
considered a logic 1.
Valid EOD Symbol
See Figure 4-9(4). If the passive-to-active received transition beginning the
next data bit (or symbol) occurs between c and d, the current symbol would be
considered a valid end-of-data symbol (EOD).
300 µs
280 µs
ACTIVE
PASSIVE
ACTIVE
PASSIVE
(1) VALID EOF SYMBOL
a
b
(2) VALID EOF+
IFS SYMBOL
c
d
Figure 4-10. J1850 VPW Received Passive
EOF and IFS Symbol Times
Valid EOF and IFS Symbol
In Figure 4-10(1), if the passive-to-active received transition beginning the SOF
symbol of the next message occurs between a and b, the current symbol will be
considered a valid end-of-frame (EOF) symbol.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor