MC68HC08AS32 Datasheet, PDF (169/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

To allow software to clear status bits during a break interrupt, write a logic 1 to the
BCFE bit. If a status bit is cleared during the break state, it remains cleared when
the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE bit. With
BCFE at logic 0 (its default state), software can read and write I/O registers during
the break state without affecting status bits. Some status bits have a 2-step
read/write clearing procedure. If software does the first step on such a bit before
the break, the bit cannot change during the break state as long as BCFE is at logic
0. After the break, doing the second step clears the status bit.
12.7 I/O Signals
Port E shares two of its pins with the SCI module. The two SCI I/O pins are:
• PTE0/TxD — Transmit data
• PTE1/RxD — Receive data
12.7.1 PTE0/TxD (Transmit Data)
The PTE0/TxD pin is the serial data output from the SCI transmitter. The SCI
shares the PTE0/TxD pin with port E. When the SCI is enabled, the PTE0/TxD pin
is an output regardless of the state of the DDRE0 bit in data direction register E
(DDRE).
12.7.2 PTE1/RxD (Receive Data)
The PTE1/RxD pin is the serial data input to the SCI receiver. The SCI shares the
PTE1/RxD pin with port E. When the SCI is enabled, the PTE1/RxD pin is an input
regardless of the state of the DDRE1 bit in data direction register E (DDRE).
12.8 I/O Registers
These I/O registers control and monitor SCI operation:
• SCI control register 1 (SCC1)
• SCI control register 2 (SCC2)
• SCI control register 3 (SCC3)
• SCI status register 1 (SCS1)
• SCI status register 2 (SCS2)
• SCI data register (SCDR)
• SCI baud rate register (SCBR)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
169