MC68HC08AS32 Datasheet, PDF (161/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

12.3.5 Break Characters
Writing a logic 1 to the send break bit, SBK (SCC2), loads the transmit shift register
with a break character. A break character contains all logic 0s and has no start,
stop, or parity bit. Break character length depends on the M bit (SCC1). As long as
SBK is at logic 1, transmitter logic continuously loads break characters into the
transmit shift register. After software clears the SBK bit, the shift register finishes
transmitting the last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the recognition of the
start bit of the next character.
The SCI recognizes a break character when a start bit is followed by eight or nine
logic 0 data bits and a logic 0 where the stop bit should be. Receiving a break
character has the following effects on SCI registers:
• Sets the framing error bit (FE) in SCS1
• Sets the SCI receiver full bit (SCRF) in SCS1
• Clears the SCI data register (SCDR)
• Clears the R8 bit in SCC3
• Sets the break flag bit (BKF) in SCS2
• May set the overrun (OR), noise flag (NF), parity error (PE), or reception in
progress flag (RPF) bits
12.3.6 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle
character length depends on the M bit (mode character length) in SCC1. The
preamble is a synchronizing idle character that begins every transmission.
If the TE bit (transmitter enable) is cleared during a transmission, the PTE0/TxD pin
becomes idle after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be sent after
the character currently being transmitted.
NOTE:
When a break sequence is followed immediately by an idle character, this SCI
design exhibits a condition in which the break character length is reduced by one
half bit time. In this instance, the break sequence will consist of a valid start bit,
eight or nine data bits (as defined by the M bit in SCC1) of logic 0, and one half data
bit length of logic 0 in the stop bit position followed immediately by the idle
character. To ensure a break character of the proper length is transmitted, always
queue up a byte of data to be transmitted while the final break sequence is in
progress.
When queueing an idle character, return the TE bit to logic 1 before the stop bit of
the current character shifts out to the PTE0/TxD pin. Setting TE after the stop bit
appears on PTE0/TxD causes loss of data previously written to the SCDR.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
161