MC68HC08AS32 Datasheet, PDF (67/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Inter-Frame Separation Symbol (IFS)
The IFS symbol is defined as a passive period 300 µs in length. The 20-µs IFS
symbol contains no transition, since when used it always appends to an EOF
symbol (see Figure 4-8(g)).
Idle
An idle is defined as a passive period greater than 300 µs in length.
4.4.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the J1850 bus have
been defined to allow for variations in oscillator frequencies. In many cases the
maximum time allowed to define a data bit or symbol is equal to the minimum time
allowed to define another data bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol is being
received is equal to a single period of the MUX interface clock (t_BDLC), an apparent
separation in these maximum time/minimum time concurrences equal to one cycle
of t_BDLC occurs.
This one clock resolution allows the BDLC to differentiate properly between the
different bits and symbols. This is done without reducing the valid window for
receiving bits and symbols from transmitters onto the J1850 bus which have
varying oscillator frequencies.
64 µs
200 µs
128 µs
ACTIVE
(1) INVALID PASSIVE BIT
PASSIVE
a
ACTIVE
(2) VALID PASSIVE LOGIC 0
PASSIVE
a
b
ACTIVE
(3) VALID PASSIVE LOGIC 1
PASSIVE
ACTIVE
b
c
(4) VALID EOD SYMBOL
PASSIVE
c
d
Figure 4-9. J1850 VPW Received Passive Symbol Times
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
67