MC68HC08AS32 Datasheet, PDF (111/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

6.3.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 6.4 COP Control
Register) clears the COP counter and clears bits 12 through 4 of the SIM counter.
Reading the COP control register returns the reset vector.
6.3.4 Internal Reset Resources
An internal reset clears the SIM counter and the COP counter. (See 13.3.2 Active
Resets from Internal Sources.)
6.3.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data bus. A
reset vector fetch clears the SIM counter.
6.3.6 COPD (COP Disable)
The COPD bit reflects the state of the COP disable bit (COPD) in the MOR register
($001F). This signal disables COP-generated resets when asserted. (See Section
10. Mask Options.)
6.3.7 COPS (COP Short Timeout)
The COPS bit selects the state of the COP short timeout bit (COPS) in the MOR
register ($001F). Timeout periods can be (2¹⁸ –2⁴⁾ or (2¹³ –2⁴⁾ CGMXCLK cycles.
(See 10.3 Mask Option Register.)
6.4 COP Control Register
The COP control register is located at address $FFFF and overlaps the reset
vector. Writing any value to $FFFF clears the COP counter and starts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF
Bit 7
6
Read:
Write:
Reset:
5
4
3
2
Low byte of reset vector
Clear COP counter
Unaffected by reset
1
Bit 0
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate CPU interrupt requests.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
111