MC68HC08AS32 Datasheet, PDF (76/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

4.5.5.5 Summary
Table 4-1. BDLC J1850 Bus Error Summary
Error Condition
Transmission error
Cyclical redundancy check (CRC) error
Invalid symbol: BDLC receives invalid
bits (noise)
Framing error
Bus short to V_DD
Bus short to GND
BDLC receives BREAK symbol.
BDLC Function
For invalid bits or framing symbols on non-byte boundaries, invalid symbol
interrupt will be generated. BDLC stops transmission.
CRC error interrupt will be generated. The BDLC will wait for SOF.
The BDLC will abort transmission immediately. Invalid symbol interrupt will
be generated.
Invalid symbol interrupt will be generated. The BDLC will wait for
start-of-frame (SOF).
The BDLC will not transmit until the bus is idle.
Thermal overload will shut down physical interface. Fault condition is
reflected in BSVR as an invalid symbol.
The BDLC will wait for the next valid SOF. Invalid symbol interrupt will be
generated.
4.6 BDLC CPU Interface
The CPU interface provides the interface between the CPU and the BDLC and
consists of five user registers.
• BDLC analog and roundtrip delay register (BARD)
• BDLC control register 1 (BCR1)
• BDLC control register 2 (BCR2)
• BDLC state vector register (BSVR)
• BDLC data register (BDR)
TO CPU
Data Sheet
76
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-16. BDLC Block Diagram
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor