MC68HC08AS32 Datasheet, PDF (81/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

RX4XE — Receive 4X Enable Bit
This bit determines if the BDLC operates at normal transmit and receive speed
(10.4 kbps) or receive only at 41.6 kbps. This feature is useful for fast download
of data into a J1850 node for diagnostic or factory programming of the node.
1 = When set, the BDLC is put in 4X receive-only operation.
0 = When cleared, the BDLC transmits and receives at 10.4 kbps.
NBFS — Normalization Bit Format Select Bit
This bit controls the format of the normalization bit (NB). (See Figure 4-20.) SAE
J1850 strongly encourages using an active long (logic 0) for in-frame responses
containing cyclical redundancy check (CRC) and an active short (logic 1) for
in-frame responses without CRC.
1 = NB that is received or transmitted is a 0 when the response part of an
in-frame response (IFR) ends with a CRC byte. NB that is received or
transmitted is a 1 when the response part of an in-frame response (IFR)
does not end with a CRC byte.
0 = NB that is received or transmitted is a 1 when the response part of an
in-frame response (IFR) ends with a CRC byte. NB that is received or
transmitted is a 0 when the response part of an in-frame response (IFR)
does not end with a CRC byte.
TEOD — Transmit End of Data Bit
This bit is set by the programmer to indicate the end of a message is being sent
by the BDLC. It will append an 8-bit CRC after completing transmission of the
current byte. This bit also is used to end an in-frame response (IFR). If the
transmit shadow register is full when TEOD is set, the CRC byte will be
transmitted after the current byte in the Tx shift register and the byte in the Tx
shadow register have been transmitted. (See 4.5.3 Rx and Tx Shadow
Registers for a description of the transmit shadow register.) Once TEOD is set,
the transmit data register empty flag (TDRE) in the BDLC state vector register
(BSVR) is cleared to allow lower priority interrupts to occur. (See 4.6.4 BDLC
State Vector Register.)
1 = Transmit end-of-data (EOD) symbol
0 = The TEOD bit will be cleared automatically at the rising edge of the first
CRC bit that is sent or if an error is detected. When TEOD is used to end
an IFR transmission, TEOD is cleared when the BDLC receives back a
valid EOD symbol or an error condition occurs.
TSIFR, TMIFR1, and TMIFR0 — Transmit In-Frame Response Control Bits
These three bits control the type of in-frame response being sent. The
programmer should not set more than one of these control bits to a 1 at any
given time. However, if more than one of these three control bits are set to 1,
the priority encoding logic will force these register bits to a known value as
shown in Table 4-4. For example, if 011 is written to TSIFR, TMIFR1, and
TMIFR0, then internally they will be encoded as 010. However, when these bits
are read back, they will read 011.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
81