MC68HC08AS32 Datasheet, PDF (176/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with
SCRF set and then reading the SCDR. Reset clears SCRF.
1 = Received data available in SCDR
0 = Data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear
on the receiver input. IDLE generates an SCI error CPU interrupt request if the
ILIE bit in SCC2 also is set and the DMARE bit in SCC3 is clear. Clear the IDLE
bit by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the SCRF bit
before an idle condition can set the IDLE bit. Also, after the IDLE bit has been
cleared, a valid character must again set the SCRF bit before an idle condition
can set the IDLE bit. Reset clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)
OR — Receiver Overrun Bit
This clearable, read-only bit is set when software fails to read the SCDR before
the receive shift register receives the next character. The OR bit generates an
SCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in
the shift register is lost, but the data already in the SCDR is not affected. Clear
the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset
clears the OR bit.
1 = Receive shift register full and SCRF = 1
0 = No receiver overrun
Software latency may allow an overrun to occur between reads of SCS1 and
SCDR in the flag-clearing sequence. Figure 12-12 shows the normal
flag-clearing sequence and an example of an overrun caused by a delayed
flag-clearing sequence. The delayed read of SCDR does not clear the OR bit
because OR was not set when SCS1 was read. Byte 2 caused the overrun and
is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of
byte 2.
In applications that are subject to software latency or in which it is important to
know which byte is lost due to an overrun, the flag-clearing routine can check
the OR bit in a second read of SCS1 after reading the data register.
NF — Receiver Noise Flag Bit
This clearable, read-only bit is set when the SCI detects noise on the PTE1/RxD
pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also
set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears
the NF bit.
1 = Noise detected
0 = No noise detected
Data Sheet
176
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor