MC68HC08AS32 Datasheet, PDF (209/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

14.5.3 Transmission Format When CPHA = 1
Figure 14-7 shows an SPI transmission in which CPHA (SPCR) is logic 1. The
figure should not be used as a replacement for data sheet parametric information.
Two waveforms are shown for SCK: one for CPOL = 0 and another for CPOL = 1.
The diagram may be interpreted as a master or slave timing diagram since the
serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI)
pins are directly connected between the master and the slave. The MISO signal is
the output from the slave, and the MOSI signal is the output from the master. The
SS line is the slave select input to the slave. The slave SPI drives its MISO output
only when its slave select input (SS) is at logic 0, so that only the selected slave
drives to the master. The SS pin of the master is not shown but is assumed to be
inactive. The SS pin of the master must be high or must be reconfigured as
general-purpose I/O not affecting the SPI. (See 14.6.2 Mode Fault Error.) When
CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge.
Therefore, the slave uses the first SPSCK edge as a start transmission signal. The
SS pin can remain low between transmissions. This format may be preferable in
systems having only one master and only one slave driving the MISO data line.
When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning
of the transmission. This causes the SPI to leave its idle state and begin driving the
MISO pin with the MSB of its data. Once the transmission begins, no new data is
allowed into the shift register from the transmit data register. Therefore, the SPI
data register of the slave must be loaded with transmit data before the first edge of
SPSCK. Any data written after the first edge is stored in the transmit data register
and transferred to the shift register after the current transmission.
SCK CYCLE #
FOR REFERENCE
1
2
3
4
5
6
7
8
SCK CPOL = 0
SCK CPOL =1
MOSI
FROM MASTER
MISO
FROM SLAVE
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
LSB
SS TO SLAVE
CAPTURE STROBE
Figure 14-7. Transmission Format (CPHA = 1)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
209