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MC68HC08AS32 Datasheet, PDF (265/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)
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17.4 5.0-Volt DC Electrical Characteristics
Characteristic(1)
Output high voltage
(ILoad = –2.0 mA) All Ports, RST
Output low voltage
(ILoad = 1.6 mA) All Ports, RST
Input high voltage
All Ports, IRQs, RESET, OSC1
Symbol
VOH
VOL
VIH
Min
VDD –0.8
Typ(2)
—
—
—
0.7 x VDD
—
Max
—
0.4
VDD
Unit
V
V
V
Input low voltage
All Ports, IRQs, RESET, OSC1
VIL
VSS
—
0.3 x VDD
V
VDD + VDDA/VDDAREF supply current
Run(3)
Wait(4)
Stop(5)
25°C
–40°C to +105°C
–40°C to +125°C
25°C with LVI enabled
–40°C to +105°C with LVI enabled
30
mA
—
—
—
—
15
mA
IDD
5
µA
—
—
50
µA
—
—
100
µA
—
—
400
µA
—
—
500
µA
I/O ports Hi-Z leakage current
Input current
Capacitance
Ports (as input or output)
Low-voltage reset inhibit
Low-voltage reset inhibit/recover hysteresis
POR rearm voltage(6)
POR reset voltage(7)
POR rise time ramp rate(8)
High COP disable voltage(9)
IL
IIN
COUT
CIN
VLVF
HLVI
VPOR
VPORRST
RPOR
VHI
—
—
—
—
3.7
50
0
0
0.02
VDD
—
±1
µA
—
±1
µA
—
—
12
8
pF
4.1
4.45
V
150
—
mV
—
200
mV
—
800
mV
—
—
V/ms
VDD + 2
V
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 V from rail. No dc loads.
Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run
IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fOP = 8.4 MHz). All inputs 0.2 Vdc from rail. No dc loads. Less
than 100 pF on all outputs, CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD.
Measured with all modules enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
9. See 6.8 COP Module During Break Interrupts.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
265
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