MC68HC08AS32 Datasheet, PDF (70/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

Valid Active Logic 1
In Figure 4-11(2), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between a and b, the current bit would be considered
a logic 1.
Valid Active Logic 0
In Figure 4-11(3), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between b and c, the current bit would be considered
a logic 0.
Valid SOF Symbol
In Figure 4-11(4), if the active-to-passive received transition beginning the next
data bit (or symbol) occurs between c and d, the current symbol would be
considered a valid SOF symbol.
Valid BREAK Symbol
In Figure 4-12, if the next active-to-passive received transition does not occur
until after e, the current symbol will be considered a valid BREAK symbol. A
BREAK symbol should be followed by a start-of-frame (SOF) symbol beginning
the next message to be transmitted onto the J1850 bus. See 4.4.2 J1850 Frame
Format for BDLC response to BREAK symbols.
240 µs
ACTIVE
PASSIVE
(2) VALID BREAK SYMBOL
e
Figure 4-12. J1850 VPW Received BREAK Symbol Times
4.4.5 Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive
manner, allowing the message with the highest priority to be transmitted, while any
transmitters which lose arbitration simply stop transmitting and wait for an idle bus
to begin transmitting again.
If the BDLC wants to transmit onto the J1850 bus, but detects that another
message is in progress, it waits until the bus is idle. However, if multiple nodes
begin to transmit in the same synchronization window, message arbitration will
occur beginning with the first bit after the SOF symbol and will continue with each
bit thereafter.
Data Sheet
70
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor