MC68HC08AS32 Datasheet, PDF (57/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
Use of the BDLC module in message networking fully implements the SAE
Standard J1850 Class B Data Communication Network Interface specification.
It is recommended that the reader be familiar with the SAE J1850 document and
ISO Serial Communication document prior to proceeding with this section of the
MC68HC08AS32 specification.
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
BDLC
TO J1850 BUS
Figure 4-2. BDLC Block Diagram
Addr.
Register Name
$003B
BDLC Analog and Roundtrip ^Read:
Delay Register (BARD) Write:
See page 77. _Reset:
Read:
$003C
BDLC Control Register 1 (BCR1)
See page 78.
Write:
Reset:
$003D
BDLC Control Register 2 ^Read:
(BCR2) Write:
See page 80. _Reset:
$003E
BDLC State Vector Register ^Read:
(BSVR) Write:
See page 85. _Reset:
$003F
BDLC Data Register ^Read:
(BDR) Write:
See page 87. _Reset:
Bit 7
ATE
1
IMSG
1
ALOOP
1
0
R
0
BD7
R
6
RXPOL
1
CLKS
1
DLOOP
1
0
R
0
BD6
5
0
R
0
R1
1
RX4XE
0
I3
R
0
BD5
= Reserved
4
3
0
R
BO3
0
0
0
R0
R
0
0
NBFS
TEOD
0
0
I2
I1
R
R
0
0
BD4
BD3
Unaffected by reset
Figure 4-3. BDLC I/O Register Summary
2
BO2
1
0
R
0
TSIFR
0
I0
R
0
BD2
1
Bit 0
BO1
BO0
1
1
IE
WCM
0
0
TMIFR1 TMIFR0
0
0
0
0
R
R
0
0
BD1
BD0
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
57