MC68HC08AS32 Datasheet, PDF (153/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

11.7.2 Data Direction Register F
Data direction register F determines whether each port F pin is an input or an
output. Writing a logic 1 to a DDRF bit enables the output buffer for the
corresponding port F pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$000D
Bit 7
6
5
0
0
0
R
R
R
0
0
0
R
= Reserved
4
3
2
1
0
R
DDRF3 DDRF2 DDRF1
0
0
0
0
Figure 11-18. Data Direction Register F (DDRF)
Bit 0
DDRF0
0
NOTE:
DDRF[3:0] — Data Direction Register F Bits
These read/write bits control port F data direction. Reset clears DDRF[3:0],
configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
Avoid glitches on port F pins by writing to the port F data register before changing
data direction register F bits from 0 to 1.
Figure 11-19 shows the port F I/O logic.
READ DDRF ($000D)
WRITE DDRF ($000D)
RESET
DDRFx
WRITE PTF ($0009)
PTFx
PTFx
READ PTF ($0009)
Figure 11-19. Port F I/O Circuit
When bit DDRFx is a logic 1, reading address $0009 reads the PTFx data latch.
When bit DDRFx is a logic 0, reading address $0009 reads the voltage level on the
pin. The data latch can always be written, regardless of the state of its data
direction bit. Table 11-6 summarizes the operation of the port F pins.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
153