MC68HC08AS32 Datasheet, PDF (167/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

12.3.13 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in
an incoming character, it sets the framing error bit, FE, in SCS1. The FE flag is set
at the same time that the SCRF bit (SCS1) is set. A break character that has no
stop bit also sets the FE bit.
12.3.14 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in
multiple-receiver systems, the receiver can be put into a standby state. Setting the
receiver wakeup bit, RWU (SCC2), puts the receiver into a standby state during
which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the
PTE1/RxD pin can bring the receiver out of the standby state:
• Address mark — An address mark is a logic 1 in the most significant bit
position of a received character. When the WAKE bit is set, an address mark
wakes the receiver from the standby state by clearing the RWU bit. The
address mark also sets the SCI receiver full bit, SCRF. Software can then
compare the character containing the address mark to the user-defined
address of the receiver. If they are the same, the receiver remains awake
and processes the characters that follow. If they are not the same, software
can set the RWU bit and put the receiver back into the standby state.
• Idle input line condition — When the WAKE bit is clear, an idle character on
the PTE1/RxD pin wakes the receiver from the standby state by clearing the
RWU bit. The idle character that wakes the receiver does not set the
receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type
bit, ILTY, determines whether the receiver begins counting logic 1s as idle
character bits after the start bit or after the stop bit.
NOTE: Clearing the WAKE bit after the PTE1/RxD pin has been idle may cause the
receiver to wake up immediately.
12.4 Receiver Interrupts
The following sources can generate CPU interrupt requests from the SCI receiver:
• SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive
shift register has transferred a character to the SCDR. SCRF can generate
a receiver CPU interrupt request. Setting the SCI receive interrupt enable
bit, SCRIE (SCC2), enables the SCRF bit to generate receiver CPU
interrupts.
• Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive
logic 1s shifted in from the PTE1/RxD pin. The idle line interrupt enable bit,
ILIE (SCC2), enables the IDLE bit to generate CPU interrupt requests.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
167