MC68HC08AS32 Datasheet, PDF (236/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
cause the compare to be missed. The TIM may pass the new value before it is
written to the timer channel (TCHxH/TCHxL) registers.
Use the following methods to synchronize unbuffered changes in the PWM pulse
width on channel x:
• When changing to a shorter pulse width, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current pulse. The
interrupt routine has until the end of the PWM period to write the new value.
• When changing to a longer pulse width, enable TIM overflow interrupts and
write the new value in the TIM overflow interrupt routine. The TIM overflow
interrupt occurs at the end of the current PWM period. Writing a larger value
in an output compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation
and removes the ability of the channel to self-correct in the event of software error
or noise. Toggling on output compare also can cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
15.3.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose output
appears on the PTE2/TCH0 pin. The TIM channel registers of the linked pair
alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links
channel 0 and channel 1. The TIM channel 0 registers initially control the pulse
width on the PTE2/TCH0 pin. Writing to the TIM channel 1 registers enables the
TIM channel 1 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers
(0 or 1) that control the pulse width are the ones written to last. TSC0 controls and
monitors the buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, PTE3/TCH1, is
available as a general-purpose I/O pin.
Channels 2 and 3 can be linked to form a buffered PWM channel whose output
appears on the PTF0/TCH2 pin. The TIM channel registers of the linked pair
alternately control the pulse width of the output.
Setting the MS2B bit in TIM channel 2 status and control register (TSC2) links
channel 2 and channel 3. The TIM channel 2 registers initially control the pulse
width on the PTF0/TCH2 pin. Writing to the TIM channel 3 registers enables the
TIM channel 3 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers
(2 or 3) that control the pulse width are the ones written to last. TSC2 controls and
monitors the buffered PWM function, and TIM channel 3 status and control register
Data Sheet
236
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor