MC68HC08AS32 Datasheet, PDF (212/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

to hang in wait mode. If the OVRF is enabled to generate an interrupt, it can pull
the MCU out of wait mode instead.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an
overflow condition. Figure 14-9 shows how it is possible to miss an overflow.
BYTE 1
1
BYTE 2
4
BYTE 3
6
BYTE 4
8
SPRF
OVRF
READ SPSCR
2
5
READ SPDR
3
7
1 BYTE 1 SETS SPRF BIT.
5 CPU READS SPSCR WITH SPRF BIT SET
2 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
AND OVRF BIT CLEAR.
6 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 BYTE 2 SETS SPRF BIT.
7 CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
8 BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS SET. BYTE 4 IS LOST.
Figure 14-9. Missed Read of Overflow Condition
The first part of Figure 14-9 shows how to read the SPSCR and SPDR to clear the
SPRF without problems. However, as illustrated by the second transmission
example, the OVRF flag can be set in between the time that SPSCR and SPDR are
read.
In this case, an overflow can be easily missed. Since no more SPRF interrupts can
be generated until this OVRF is serviced, it will not be obvious that bytes are being
lost as more transmissions are completed. To prevent this, either enable the OVRF
interrupt or do another read of the SPSCR after the read of the SPDR. This ensures
that the OVRF was not set before the SPRF was cleared and that future
transmissions will complete with an SPRF interrupt. Figure 14-10 illustrates this
process. Generally, to avoid this second SPSCR read, enable the OVRF to the
CPU by setting the ERRIE bit (SPSCR).
Data Sheet
212
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor