MC68HC08AS32 Datasheet, PDF (74/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

4.5.5 State Machine
All of the functions associated with performing the protocol are executed or
controlled by the state machine. The state machine is responsible for framing,
collision detection, arbitration, CRC generation/checking, and error detection. The
following sections describe the BDLC’s actions in a variety of situations.
4.5.5.1 4X Mode
The BDLC can exist on the same J1850 bus as modules which use a special 4X
(41.6 kbps) mode of J1850 variable pulse width modulation (VPW) operation. The
BDLC cannot transmit in 4X mode, but can receive messages in 4X mode, if the
RX4X bit is set in BCR2 register. If the RX4X bit is not set in the BCR2 register, any
4X message on the J1850 bus is treated as noise by the BDLC and is ignored.
4.5.5.2 Receiving a Message in Block Mode
Although not a part of the SAE J1850 protocol, the BDLC does allow for a special
block mode of operation of the receiver. As far as the BDLC is concerned, a block
mode message is simply a long J1850 frame that contains an indefinite number of
data bytes. All of the other features of the frame remain the same, including the
SOF, CRC, and EOD symbols.
Another node wishing to send a block mode transmission must first inform all other
nodes on the network that this is about to happen. This is usually accomplished by
sending a special predefined message.
4.5.5.3 Transmitting a Message in Block Mode
A block mode message is transmitted inherently by simply loading the bytes one
by one into the BDR register until the message is complete. The programmer
should wait until the TDRE flag (see 4.6.4 BDLC State Vector Register) is set
prior to writing a new byte of data into the BDR register. The BDLC does not contain
any predefined maximum J1850 message length requirement.
4.5.5.4 J1850 Bus Errors
The BDLC detects several types of transmit and receive errors which can occur
during the transmission of a message onto the J1850 bus.
Transmission Error
If the message transmitted by the BDLC contains invalid bits or framing symbols
on non-byte boundaries, this constitutes a transmission error. When a
transmission error is detected, the BDLC immediately will cease transmitting.
The error condition ($1C) is reflected in the BSVR register (see Table 4-5). If
the interrupt enable bit (IE in BCR1) is set, a CPU interrupt request from the
BDLC is generated.
Data Sheet
74
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor