MC68HC08AS32 Datasheet, PDF (134/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

V_DD
DLEOTEWCVT^DO^DR
LVIPWR
FROM CONFIG
CPU CLOCK
V_DD > V_LVIR = 0
V_DD < V_LVIF = 1
DIGITAVL^DDFILTER
FROM CONFIG
LVIRST
ANLGTRIP
STOP MODE
FILTER BYPASS
LVIOUT
LVISTOP
FROM CONFIG
Figure 9-1. LVI Module Block Diagram
LVI RESET
9.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_LVIF level, software can
monitor V_DD by polling the LVIOUT bit. In the MOR register, the LVIPWR bit must
be at logic1 to enable the LVI module, and the LVIRST bit must be at logic 0 to
disable LVI resets.
9.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_LVIF level, enabling LVI
resets allows the LVI module to reset the MCU when V_DD falls to the V_LVIF level
and remains at or below that level for nine or more consecutive CPU cycles. In the
MOR register, the LVIPWR and LVIRST bits must be at logic 1 to enable the LVI
module and to enable LVI resets.
9.3.3 False Reset Protection
The V_DD pin level is digitally filtered to reduce false resets due to power supply
noise. In order for the LVI module to reset the MCU,V_DD must remain at or below
the V_LVIF level for nine or more consecutive CPU cycles. V_DD must be above V_LVIR
for only one CPU cycle to bring the MCU out of reset.
Data Sheet
134
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor