MC68HC08AS32 Datasheet, PDF (223/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

14.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following conditions:
• Receive data register full
• Failure to clear SPRF bit before next byte is received (overflow error)
• Inconsistent logic level on SS pin (mode fault error)
• Transmit data register empty
The SPI status and control register also contains bits that perform these functions:
• Enable error interrupts
• Enable mode fault error detection
• Select master SPI baud rate
Address:
Read:
Write:
Reset:
$0011
Bit 7
SPRF
R
0
R
6
ERRIE
0
= Reserved
5
OVRF
R
0
4
MODF
R
0
3
SPTE
R
1
2
MODFEN
0
1
SPR1
0
Figure 14-15. SPI Status and Control Register (SPSCR)
Bit 0
SPR0
0
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift
register to the receive data register. SPRF generates a CPU interrupt request if
the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status
and control register with SPRF set and then reading the SPI data register. Any
read of the SPI data register clears the SPRF bit, and reset also clears the
SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error Interrupt Enable Bit
This bit enables the MODF and OVRF flags to generate CPU interrupt requests.
Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
223