MC68HC08AS32 Datasheet, PDF (135/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

9.4 LVI Status Register
The LVI status register flags V_DD voltages below the V_LVIF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write: R
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 9-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the V_LVIF
voltage or 32 to 40 CGMXCLK cycles. (See Table 9-1.) Reset clears the
LVIOUT bit.
At Level:
V_DD > V_LVIR
V_DD < V_LVIF
V_DD < V_LVIF
V_DD < V_LVIF
V_LVIF < V_DD < V_LVIR
Table 9-1. LVIOUT Bit Indication
V_DD
For Number of CGMXCLK Cycles:
Any
< 32 CGMXCLK Cycles
Between 32 and 40
CGMXCLK Cycles
> 40 CGMXCLK Cycles
Any
LVIOUT
0
0
0 or 1
1
Previous Value
9.5 LVI Interrupts
The LVI module does not generate interrupt requests.
9.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low-power standby modes.
9.6.1 Wait Mode
With the LVIPWR bit in the MOR register programmed to logic 1, the LVI module
is active after a WAIT instruction.
With the LVIRST bit in the MOR register programmed to logic 1, the LVI module
can generate a reset and bring the MCU out of wait mode.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
135