MC68HC08AS32 Datasheet, PDF (217/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

14.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI
enable bit (SPE) is low. Whenever SPE is low, the following occurs:
• The SPTE flag is set.
• Any transmission currently in progress is aborted.
• The shift register is cleared.
• The SPI state counter is cleared, making it ready for a new complete
transmission.
• All the SPI port logic is defaulted back to being general-purpose I/O.
These additional items are reset only by a system reset:
• All control bits in the SPCR register
• All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0)
• The status flags SPRF, OVRF, and MODF
By not resetting the control bits when SPE is low, the user can clear SPE between
transmissions without having to reset all control bits when SPE is set back to high
for the next transmission.
By not resetting the SPRF, OVRF, and MODF flags, the user can still service these
interrupts after the SPI has been disabled. The user can disable the SPI by writing
0 to the SPE bit. The SPI also can be disabled by a mode fault occurring in an SPI
that was configured as a master with the MODFEN bit set.
14.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power standby modes.
14.10.1 Wait Mode
The SPI module remains active after the execution of a WAIT instruction. In wait
mode, the SPI module registers are not accessible by the CPU. Any enabled CPU
interrupt request from the SPI module can bring the MCU out of wait mode.
If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT instruction.
To exit wait mode when an overflow condition occurs, enable the OVRF bit to
generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE).
(See 14.7 Interrupts.)
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
217