MC68HC08AS32 Datasheet, PDF (237/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

NOTE:
(TSC3) is unused. While the MS2B bit is set, the channel 3 pin, PTF1/TCH3, is
available as a general-purpose I/O pin.
Channels 4 and 5 can be linked to form a buffered PWM channel whose output
appears on the PTF2/TCH4 pin. The TIM channel registers of the linked pair
alternately control the pulse width of the output.
Setting the MS4B bit in TIM channel 4 status and control register (TSC4) links
channel 4 and channel 5. The TIM channel 4 registers initially control the pulse
width on the PTF2/TCH4 pin. Writing to the TIM channel 5 registers enables the
TIM channel 5 registers to synchronously control the pulse width at the beginning
of the next PWM period. At each subsequent overflow, the TIM channel registers
(4 or 5) that control the pulse width are the ones written to last. TSC4 controls and
monitors the buffered PWM function, and TIM channel 5 status and control register
(TSC5) is unused. While the MS4B bit is set, the channel 5 pin, PTF3/TCH5, is
available as a general-purpose I/O pin.
In buffered PWM signal generation, do not write pulse width values to the currently
active channel registers. User software should track the currently active channel to
prevent writing a new value to the active channel. Writing to the active channel
registers is the same as generating unbuffered PWM signals.
15.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals,
use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit,
TRST.
2. In the TIM counter modulo registers (TMODH–TMODL), write the value for
the required PWM period.
3. In the TIM channel x registers (TCHxH–TCHxL), write the value for the
required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0–1 (for unbuffered output compare or PWM signals) or 1–0 (for
buffered output compare or PWM signals) to the mode select bits,
MSxB–MSxA. (See Table 15-2.)
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1–0 (to clear output on compare) or 1–1 (to set output on
compare) to the edge/level select bits, ELSxB–ELSxA. The output
action on compare must force the output to the complement of the
pulse width level. (See Table 15-2.)
NOTE: In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
237