MC68HC08AS32 Datasheet, PDF (80/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

WCM — Wait Clock Mode Bit
This bit determines the operation of the BDLC during CPU wait mode. See 4.7.2
Stop Mode and 4.7.1 Wait Mode for more details on its use.
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
4.6.3 BDLC Control Register 2
This register controls transmitter operations of the BDLC. It is recommended that
BSET and BCLR instructions be used to manipulate data in this register to ensure
that the register’s content does not change inadvertently.
Address:
Read:
Write:
Reset:
$003D
Bit 7
ALOOP
1
6
DLOOP
1
5
RX4XE
0
4
NBFS
0
3
TEOD
0
2
TSIFR
0
1
TMIFR1
0
Figure 4-19. BDLC Control Register 2 (BCR2)
Bit 0
TMIFR0
0
ALOOP — Analog Loopback Mode Bit
This bit determines whether the J1850 bus will be driven by the analog physical
interface’s final drive stage. The programmer can use this bit to reset the BDLC
state machine to a known state after the off-chip analog transceiver is placed in
loopback mode. When the user clears ALOOP, to indicate that the off-chip
analog transceiver is no longer in loopback mode, the BDLC waits for an EOF
symbol before attempting to transmit.
1 = Input to the analog physical interface’s final drive stage is looped back to
the BDLC receiver. The J1850 bus is not driven.
0 = The J1850 bus will be driven by the BDLC. After the bit is cleared, the
BDLC requires the bus to be idle for a minimum of end-of-frame symbol
time (t_TRV4) before message reception or a minimum of inter-frame
symbol time (t_TRV6) before message transmission. (See 17.15 BDLC
Receiver VPW Symbol Timings.)
DLOOP — Digital Loopback Mode Bit
This bit determines the source to which the digital receive input (BDRxD) is
connected and can be used to isolate bus fault conditions (see Figure 4-15).
If a fault condition has been detected on the bus, this control bit allows the
programmer to connect the digital transmit output to the digital receive input. In
this configuration, data sent from the transmit buffer will be reflected back into
the receive buffer. If no faults exist in the BDLC, the fault is in the physical
interface block or elsewhere on the J1850 bus.
1 = When set, BDRxD is connected to BDTxD. The BDLC is now in digital
loopback mode.
0 = When cleared, BDTxD is not connected to BDRxD. The BDLC is taken
out of digital loopback mode and can now drive the J1850 bus normally.
Data Sheet
80
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor