MC68HC08AS32 Datasheet, PDF (188/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

13.3.1 External Pin Reset
Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a minimum of 67
CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of
the reset. See Table 13-2 for details. Figure 13-5 shows the relative timing.
Table 13-2. PIN Bit Set Timing
Reset Type
POR/LVI
All others
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
67 (64 + 3)
CGMOUT
RST
IAB PC
VECT H VECT L
Figure 13-5. External Reset Timing
13.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to
allow resetting of external peripherals. The internal reset signal IRST continues to
be asserted for an additional 32 cycles (see Figure 13-6). An internal reset can be
caused by an illegal address, illegal opcode, COP timeout, LVI, or POR (see
Figure 13-7.
NOTE:
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles during
which the SIM forces the RST pin low. The internal reset signal then follows the
sequence from the falling edge of RST shown in Figure 13-6.
IRST
RST
CGMXCLK
IAB
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
VECTOR HIGH
Figure 13-6. Internal Reset Timing
Data Sheet
188
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor