MC68HC08AS32 Datasheet, PDF (52/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

3.7.2 ADC Data Register
One 8-bit data register is provided. This register is updated each time an ADC
conversion completes.
Address: $0039
Bit 7
6
5
4
3
2
1
Bit 0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Write: R
R
R
R
R
R
R
R
Reset:
Unaffected by reset
R
= Reserved
Figure 3-4. ADC Data Register (ADR)
3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003A
Bit 7
6
5
4
3
2
1
Bit 0
Read: _ADIV2
ADIV1
ADIV0 ADICLK
0
0
0
0
Write:
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 3-5. ADC Input Clock Register (ADICLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used
by the ADC to generate the internal ADC clock. Table 3-2 shows the available
clock configurations. The ADC clock should be set to approximately 1 MHz.
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1
0
0
0
0
0
1
0
1
1
X
X = Don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
ADC input clock ÷ 1
ADC input clock ÷ 2
ADC input clock ÷ 4
ADC input clock ÷ 8
ADC input clock ÷ 16
Data Sheet
52
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor