MC68HC08AS32 Datasheet, PDF (143/280 Pages) Motorola, Inc – M68HC08 Family of 8-bit microcontroller units (MCUs)

11.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an
output. Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1
0
0
0
0
0
0
0
Figure 11-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
NOTE:
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0],
configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Avoid glitches on port B pins by writing to the port B data register before changing
data direction register B bits from 0 to 1.
Figure 11-7 shows the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 11-7. Port B I/O Circuit
When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch.
When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the
pin, or logic 0 if that particular bit is in use by the ADC. The data latch can always
be written, regardless of the state of its data direction bit. Table 11-2 summarizes
the operation of the port B pins.
MC68HC08AS32 — Rev. 4.1
Freescale Semiconductor
Data Sheet
143