MC9S12HZ256 Datasheet, PDF (75/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.3.2.10 Flash Address Registers (FADDR)
The banked FADDRHI and FADDRLO registers are the Flash address registers.
7
6
5
4
3
2
1
0
R
FADDRHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-14. Flash Address High Register (FADDRHI)
7
6
5
4
3
2
1
0
R
FADDRLO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-15. Flash Address Low Register (FADDRLO)
All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a
command write sequence, the FADDR registers will contain the mapped MCU address written.
2.3.2.11 Flash Data Registers (FDATA)
The banked FDATAHI and FDATALO registers are the Flash data registers.
7
6
5
4
3
2
1
0
R
FDATAHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-16. Flash Data High Register (FDATAHI)
7
6
5
4
3
2
1
0
R
FDATALO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-17. Flash Data Low Register (FDATALO)
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
75