MC9S12HZ256 Datasheet, PDF (452/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Field
5
CAE5
4
CAE4
3
CAE3
2
CAE2
1
CAE1
0
CAE0
Table 15-8. PWMCAE Field Descriptions
Description
Center Aligned Output Mode on Channel 5
0 Channel 5 operates in left aligned output mode.
1 Channel 5 operates in center aligned output mode.
Center Aligned Output Mode on Channel 4
0 Channel 4 operates in left aligned output mode.
1 Channel 4 operates in center aligned output mode.
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
15.3.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
7
6
5
4
3
2
1
0
R
0
0
0
CON45
CON23
CON01
PSWAI
PFRZ
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-8. PWM Control Register (PWMCTL)
Read: anytime
Write: anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 4 and 5 are concatenated, channel 4 registers become the
high-order bytes of the double-byte channel. When channels 2 and 3 are concatenated, channel 2 registers
become the high-order bytes of the double-byte channel. When channels 0 and 1 are concatenated,
channel 0 registers become the high-order bytes of the double-byte channel.
Reference Section 15.4.2.7, “PWM 16-Bit Functions,” for a more detailed description of the concatenation
PWM function.
MC9S12HZ256 Data Sheet, Rev. 2.04
452
Freescale Semiconductor