MC9S12HZ256 Datasheet, PDF (144/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5.2 Port S Input Register (PTIS)
7
6
5
4
3
2
R PTIS7
PTIS6
PTIS5
PTIS4
0
0
W
Reset
u
u
u
u
0
0
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-31. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
4.3.5.3 Port S Data Direction Register (DDRS)
1
PTIS1
u
0
PTIS0
u
R
W
Reset
7
DDRS7
0
6
5
4
3
2
0
0
DDRS6
DDRS5
DDRS4
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-32. Port S Data Direction Register (DDRS)
1
DDRS1
0
0
DDRS0
0
Read: Anytime. Write: Anytime.
This register configures port pins PS[7:4] and PS[2:0] as either input or output.
When the SPI is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data
Direction Register bits have no effect.
When the SCI0 transmitter is enabled, the PS[1] pin becomes the TXD0 output pin and the associated Data
Direction Register bit has no effect. When the SCI0 receiver is enabled, the PS[0] pin becomes the RXD0
input pin and the associated Data Direction Register bit has no effect.
If the SPI and SCI0 functions are disabled, the corresponding Data Direction Register bit reverts to control
the I/O direction of the associated pin.
Table 4-23. DDRS Field Descriptions
Field
7:4
Data Direction Port S
DDRS[7:4] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
1:0
Data Direction Port S
DDRS[1:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12HZ256 Data Sheet, Rev. 2.04
144
Freescale Semiconductor