MC9S12HZ256 Datasheet, PDF (138/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.4 Port P
Port P is associated with the Pulse Width Modulator (PWM), serial communication interface (SCI1) and
Inter-IC bus (IIC) modules. Each pin is assigned to these modules according to the following priority:
PWM > SCI1/IIC > general-purpose I/O.
When a PWM channel is enabled, the corresponding pin becomes a PWM output with the exception of
PP[5] which can be PWM input or output. Refer to the PWM block description chapter for information on
enabling and disabling the PWM channels.
When the IIC bus is enabled, the PP[5:4] pins become SCL and SDA respectively as long as the
corresponding PWM channels are disabled. Refer to the IIC block description chapter for information on
enabling and disabling the IIC bus.
When the SCI1 receiver and transmitter are enabled, the PP[2] and PP[0] pins become RXD1 and TXD1
respectively as long as the corresponding PWM channels are disabled. Refer to the SCI block description
chapter for information on enabling and disabling the SCI receiver and transmitter.
During reset, port P pins are configured as high-impedance inputs.
4.3.4.1 Port P I/O Register (PTP)
7
R
0
W
6
5
4
3
2
1
0
0
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
SCI1/IIC:
SCL
SDA
RXD1
TXD1
PWM:
PWM5
PWM4
PWM3
PWM2
PWM1
PWM0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-23. Port P I/O Register (PTP)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRPx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRPx) is set to 0 (input), a read returns the value of the pin.
The PWM function takes precedence over the general-purpose I/O function if the associated PWM
channel is enabled. The PWM channels 4-0 are outputs if the respective channels are enabled. PWM
channel 5 can be an output, or an input if the shutdown feature is enabled.
The IIC function takes precedence over the general-purpose I/O function if the IIC bus is enabled and the
corresponding PWM channels remain disabled. The SDA and SCL pins are bidirectional with outputs
configured as open-drain.
If enabled, the SCI1 transmitter takes precedence over the general-purpose I/O function, and the
corresponding TXD1 pin is configured as an output. If enabled, the SCI1 receiver takes precedence over
the general-purpose I/O function, and the corresponding RXD1 pin is configured as an input.
MC9S12HZ256 Data Sheet, Rev. 2.04
138
Freescale Semiconductor