MC9S12HZ256 Datasheet, PDF (52/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12HZ256 Device Overview
1.8.2.2 Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM
operations will be blocked.
1.8.3 Unsecuring the Microcontroller
In order to unsecure the microcontroller, the internal FLASH and EEPROM must be erased. This can be
done through an external program in expanded mode.
After the user has erased the FLASH and EEPROM, the part can be reset into special single chip mode.
This invokes a program that verifies the erasure of the internal FLASH and EEPROM. After this program
completes, the user can erase and program the FLASH security bits to the unsecured state. This is generally
done through the BDM, but the user could also change to expanded mode (by writing the mode bits
through the BDM) and jumping to an external program (again through BDM commands). Note that if the
part goes through a reset before the security bits are reprogrammed to the unsecure state, the part will be
secured again.
1.9 Low Power Modes
Consult the respective block description chapter for information on the module behavior in stop, pseudo
stop, and wait mode.
1.10 Resets and Interrupts
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts. Both local masking and CCR masking are included as listed in Table 1-11. System resets can
be generated through external control of the RESET pin, through the clock and reset generator module
CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG
and VREG block description chapters for detailed information on reset generation.
1.10.1 Vectors
Table 1-11 lists interrupt sources and vectors in default order of priority.
Table 1-11. Interrupt Vector Locations
Vector Address
0xFFFE, 0xFFFF
0xFFFC, 0xFFFD
0xFFFA, 0xFFFB
0xFFF8, 0xFFF9
0xFFF6, 0xFFF7
0xFFF4, 0xFFF5
Interrupt Source
CCR
Mask
External Reset, Power On Reset or Low None
Voltage Reset (see CRG Flags Register to
determine reset source)
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
None
None
None
SWI
XIRQ
None
X-Bit
Local Enable
None
COPCTL (CME, FCME)
COP rate select
None
None
None
HPRIO Value
to Elevate
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MC9S12HZ256 Data Sheet, Rev. 2.04
52
Freescale Semiconductor