MC9S12HZ256 Datasheet, PDF (221/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
Table 7-13. Clock Prescaler Values
Prescale Value
Total Divisor
Value
Max. Bus Clock¹
Min. Bus Clock²
00000
Divide by 2
4 MHz
1 MHz
00001
Divide by 4
8 MHz
2 MHz
00010
Divide by 6
12 MHz
3 MHz
00011
Divide by 8
16 MHz
4 MHz
00100
Divide by 10
20 MHz
5 MHz
00101
Divide by 12
24 MHz
6 MHz
00110
Divide by 14
28 MHz
7 MHz
00111
Divide by 16
32 MHz
8 MHz
01000
Divide by 18
36 MHz
9 MHz
01001
Divide by 20
40 MHz
10 MHz
01010
Divide by 22
44 MHz
11 MHz
01011
Divide by 24
48 MHz
12 MHz
01100
Divide by 26
52 MHz
13 MHz
01101
Divide by 28
56 MHz
14 MHz
01110
Divide by 30
60 MHz
15 MHz
01111
Divide by 32
64 MHz
16 MHz
10000
Divide by 34
68 MHz
17 MHz
10001
Divide by 36
72 MHz
18 MHz
10010
Divide by 38
76 MHz
19 MHz
10011
Divide by 40
80 MHz
20 MHz
10100
Divide by 42
84 MHz
21 MHz
10101
Divide by 44
88 MHz
22 MHz
10110
Divide by 46
92 MHz
23 MHz
10111
Divide by 48
96 MHz
24 MHz
11000
Divide by 50
100 MHz
25 MHz
11001
Divide by 52
104 MHz
26 MHz
11010
Divide by 54
108 MHz
27 MHz
11011
Divide by 56
112 MHz
28 MHz
11100
Divide by 58
116 MHz
29 MHz
11101
Divide by 60
120 MHz
30 MHz
11110
Divide by 62
124 MHz
31 MHz
11111
Divide by 64
128 MHz
32 MHz
1 _{Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is}
shown in this column.
2 _{Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is}
shown in this column.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
221