MC9S12HZ256 Datasheet, PDF (250/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 8 Liquid Crystal Display (LCD32F4BV1)
8.4.1.3 LCD RAM
For a segment on the LCD to be displayed, data must be written to the LCD RAM which is shown in
Section 8.3, “Memory Map and Register Definition”. The 128 bits in the LCD RAM correspond to the 128
segments that are driven by the frontplane and backplane drivers. Writing a 1 to a given location will result
in the corresponding display segment being driven with a differential RMS voltage necessary to turn the
segment ON when the LCDEN bit is set and the corresponding FP[31:0]EN bit is set. Writing a 0 to a given
location will result in the corresponding display segment being driven with a differential RMS voltage
necessary to turn the segment OFF. The LCD RAM is a dual port RAM that interfaces with the internal
address and data buses of the MCU. It is possible to read from LCD RAM locations for scrolling purposes.
When LCDEN = 0, the LCD RAM can be used as on-chip RAM. Writing or reading of the LCDEN bit
does not change the contents of the LCD RAM. After a reset, the LCD RAM contents will be
indeterminate.
8.4.1.4 LCD Driver System Enable and Frontplane Enable Sequencing
If LCDEN = 0 (LCD32F4B driver system disabled) and the frontplane enable bit, FP[31:0]EN, is set, the
frontplane driver waveform will not appear on the output until LCDEN is set. If LCDEN = 1 (LCD32F4B
driver system enabled), the frontplane driver waveform will appear on the output as soon as the
corresponding frontplane enable bit, FP[31:0]EN, in the registers FPENR0–FPENR3 is set.
8.4.1.5 LCD Bias and Modes of Operation
The LCD32F4B driver has five modes of operation:
• 1/1 duty (1 backplane), 1/1 bias (2 voltage levels)
• 1/2 duty (2 backplanes), 1/2 bias (3 voltage levels)
• 1/2 duty (2 backplanes), 1/3 bias (4 voltage levels)
• 1/3 duty (3 backplanes), 1/3 bias (4 voltage levels)
• 1/4 duty (4 backplanes), 1/3 bias (4 voltage levels)
The voltage levels required for the different operating modes are generated internally based on VLCD.
Changing VLCD alters the differential RMS voltage across the segments in the ON and OFF states,
thereby setting the display contrast.
The backplane waveforms are continuous and repetitive every frame. They are fixed within each operating
mode and are not affected by the data in the LCD RAM.
The frontplane waveforms generated are dependent on the state (ON or OFF) of the LCD segments as
defined in the LCD RAM. The LCD32F4B driver hardware uses the data in the LCD RAM to construct
the frontplane waveform to create a differential RMS voltage necessary to turn the segment ON or OFF.
The LCD duty is decided by the DUTY1 and DUTY0 bits in the LCD control register 0 (LCDCR0). The
number of bias voltage levels is determined by the BIAS bit in LCDCR0. Table 8-8 summarizes the
multiplex modes (duties) and the bias voltage levels that can be selected for each multiplex mode (duty).
The backplane pins have their corresponding backplane waveform output BP[3:0] in high impedance state
when in the OFF state as indicated in Table 8-8. In the OFF state the corresponding pins BP[3:0]can be
used for other functionality, for example as general purpose I/O ports.
MC9S12HZ256 Data Sheet, Rev. 2.04
250
Freescale Semiconductor