MC9S12HZ256 Datasheet, PDF (74/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
7
6
5
4
3
2
1
0
R
0
W
CMDB
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-12. Flash Command Register (FCMD - NVM User Mode)
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
Table 2-17. FCMD Field Descriptions
Field
Description
6-0
Flash Command — Valid Flash commands are shown in Table 2-18. Writing any command other than those
CMDB[6:0] listed in Table 2-18 sets the ACCERR flag in the FSTAT register.
Table 2-18. Valid Flash Command List
CMDB[6:0]
0x05
0x06
0x20
0x40
0x41
0x47
NVM Command
Erase Verify
Data Compress
Word Program
Sector Erase
Mass Erase
Sector Erase Abort
2.3.2.9 Flash Control Register (FCTL)
The banked FCTL register is the Flash control register.
7
6
5
4
3
2
1
0
R NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
W
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 2-13. Flash Control Register (FCTL)
All bits in the FCTL register are readable but are not writable.
The FCTL register is loaded from the Flash Configuration Field byte at $FF0E during the reset sequence,
indicated by F in Figure 2-13.
Table 2-19. FCTL Field Descriptions
Field
7-0
NV[7:0]
Description
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper
use of the NV bits.
MC9S12HZ256 Data Sheet, Rev. 2.04
74
Freescale Semiconductor