MC9S12HZ256 Datasheet, PDF (606/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 22 Module Mapping Control (MMCV4)
22.3.2 Register Descriptions
Name
INITRM
INITRG
INITEE
MISC
MTSTO
Bit 7
R
RAM15
W
R
0
W
R
EE15
W
R
0
W
R Bit 7
W
6
RAM14
REG14
EE14
0
6
5
RAM13
REG13
EE13
0
5
4
3
2
0
RAM12 RAM11
1
Bit 0
0
RAMHAL
0
0
0
REG12 REG11
0
EE12
EE11
0
EEON
0
EXSTR1 EXSTR0 ROMHM ROMON
4
3
2
1
Bit 0
MTST1
R Bit 7
6
5
4
3
2
1
Bit 0
W
MEMSIZ0
MEMSIZ1
R REG_SW0
0
EEP_SW1 EEP_SW0
0
RAM_SW2 RAM_SW1 RAM_SW0
W
R ROM_SW1 ROM_SW0
0
0
0
0
PAG_SW1 PAG_SW0
W
PPAGE
Reserved
R
0
W
R
0
W
0
PIX5
PIX4
PIX3
PIX2
PIX1
PIX0
0
0
0
0
0
0
0
= Unimplemented
Figure 22-2. MMC Register Summary
22.3.2.1 Initialization of Internal RAM Position Register (INITRM)
R
W
Reset
7
6
5
4
3
2
1
0
0
RAM15
RAM14
RAM13
RAM12
RAM11
0
0
0
0
1
0
0
= Unimplemented or Reserved
Figure 22-3. Initialization of Internal RAM Position Register (INITRM)
Read: Anytime
0
RAMHAL
1
MC9S12HZ256 Data Sheet, Rev. 2.04
606
Freescale Semiconductor