MC9S12HZ256 Datasheet, PDF (48/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12HZ256 Device Overview
1.7.1 Normal Operating Modes
These modes provide three operating configurations. Background debug is available in all three modes,
but must first be enabled for some operations by means of a BDM background command, then activated.
1.7.1.1 Normal Single-Chip Mode
There is no external expansion bus in this mode. All pins of ports A, B, E and K are general-purpose I/O
pins initially configured with internal pull-downs enabled, except port E bits 1 and 0 which are available
as general-purpose input only pins with internal pull-ups enabled.
The pins associated with port E bits 6, 5, 3, and 2 cannot be configured for their alternate functions IPIPE1,
IPIPE0, LSTRB, and R/W while the MCU is in single chip modes. In single chip modes, the associated
control bits PIPOE, LSTRE, and RDWE are reset to zero. Writing the opposite state into them in single
chip mode does not change the operation of the associated port E pins.
In normal single chip mode, the MODE register is writable one time. This allows a user program to change
the bus mode to narrow or wide expanded mode and/or turn on visibility of internal accesses.
Port E, bit 4 can be configured for a free-running E clock output by clearing NECLK=0. Typically the only
use for an E clock output while the MCU is in single chip modes would be to get a constant speed clock
for use in the external application system.
1.7.1.2 Normal Expanded Wide Mode
All pins of ports A, B, E and K are general-purpose I/O pins initially configured with internal pull-downs
enabled, except port E bits 1 and 0 which are available as general-purpose input only pins with internal
pull-ups enabled.
In expanded wide modes, ports A and B are configured as a 16-bit multiplexed address and data bus and
port E bit 4 is configured as the E clock output signal. These signals allow external memory and peripheral
devices to be interfaced to the MCU.
Port E pins other than PE4/ECLK are configured as general-purpose I/O pins. Control bits PIPOE,
NECLK, LSTRE, and RDWE in the PEAR register can be used to configure port E pins to act as bus
control outputs instead of general-purpose I/O pins.
It is possible to enable the pipe status signals on port E bits 6 and 5 by setting the PIPOE bit in PEAR, but
it would be unusual to do so in this mode. Development systems where pipe status signals are monitored
would typically use the special variation of this mode.
The port E bit 2 pin can be reconfigured as the R/W bus control signal by writing “1” to the RDWE bit in
PEAR. If the expanded system includes external devices that can be written, such as RAM, the RDWE bit
would need to be set before any attempt to write to an external location. If there are no writable resources
in the external system, PE2 can remain a general-purpose I/O pin.
The port E bit 3 pin can be reconfigured as the LSTRB bus control signal by writing “1” to the LSTRE bit
in PEAR. The default condition of this pin is a general-purpose input because the LSTRB function is not
needed in all expanded wide applications.
MC9S12HZ256 Data Sheet, Rev. 2.04
48
Freescale Semiconductor