MC9S12HZ256 Datasheet, PDF (47/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12HZ256 Device Overview
1.7 Modes of Operation
Eight possible modes determine the operating configuration of the MC9S12HZ256. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 1-10). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal.
Table 1-10. Mode Selection
MODC
0
0
X
0
1
1
1
MODB
0
0
1
1
0
0
1
MODA
0
1
0
1
0
1
1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is allowed in all other modes
but a serial command is required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Reserved for factory test
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Normal Expanded Wide, BDM allowed
There are two basic types of operating modes:
1. Normal modes: Some registers and bits are protected against accidental changes.
2. Special modes: Allow greater access to protected control registers and bits for special purposes such
as testing.
A system development and debug feature, background debug mode (BDM), is available in all modes. In
special single-chip mode, BDM is active immediately after reset.
Some aspects of port E are not mode dependent. Bit 1 of port E is a general-purpose input or the IRQ
interrupt input. IRQ can be enabled by bits in the CPU’s condition codes register but it is inhibited at reset
so this pin is initially configured as a simple input with a pull-up. Bit 0 of port E is a general-purpose input
or the XIRQ interrupt input. XIRQ can be enabled by bits in the CPU’s condition codes register but it is
inhibited at reset so this pin is initially configured as a simple input with a pull-up. The ESTR bit in the
EBICTL register is set to one by reset in any user mode. This assures that the reset vector can be fetched
even if it is located in an external slow memory device. The PE6/MODB/IPIPE1 and PE5/MODA/IPIPE0
pins act as pull-down select inputs during reset and high-impedance select inputs after reset.
The following paragraphs discuss the default bus setup and describe which aspects of the bus can be
changed after reset on a per mode basis.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
47