MC9S12HZ256 Datasheet, PDF (156/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.8 Port V
Port V is associated with the stepper stall detect (SSD3 and SSD2) and motor controller (MC3 and MC2)
modules. Each pin is assigned to these modules according to the following priority: SSD3/SSD2 >
MC3/MC2 > general-purpose I/O.
If SSD3 module is enabled, the PV[7:4] pins are controlled by the SSD3 module. If SSD3 module is
disabled, the PV[7:4] pins are controlled by the motor control PWM channels 7 and 6 (MC3).
If SSD2 module is enabled, the PV[3:0] pins are controlled by the SSD2 module. If SSD2 module is
disabled, the PV[3:0] pins are controlled by the motor control PWM channels 5 and 4 (MC2).
Refer to the SSD and MC block description chapters for information on enabling and disabling the SSD
module and the motor control PWM channels respectively.
During reset, port V pins are configured as high-impedance inputs.
4.3.8.1 Port V I/O Register (PTV)
7
R
PTV7
W
6
PTV6
5
PTV5
4
PTV4
3
PTV3
2
PTV2
1
PTV1
0
PTV0
MC: M3C1P
M3C1M
M3C0P
M3C0M
M2C1P
M2C1M
M2C0P
M2C0M
SSD3/
SSD2
M3SINP
M3SINM M3COSP M3COSM M2SINP
M2SINM M2COSP M2COSM
Reset
0
0
0
0
0
0
0
0
Figure 4-49. Port V I/O Register (PTV)
Read: Anytime. Write: anytime.
If the associated data direction bit (DDRVx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is enabled, the associated
I/O register bit (PTVx) reads “1”.
If the associated data direction bit (DDRVx) is set to 0 (input) and the slew rate is disabled, a read returns
the value of the pin.
MC9S12HZ256 Data Sheet, Rev. 2.04
156
Freescale Semiconductor