MC9S12HZ256 Datasheet, PDF (164/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.6 Interrupts
4.6.1 General
Port AD generates an edge sensitive interrupt if enabled. It offers eight I/O pins with edge triggered
interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector.
Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1)
or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or
wait mode.
A digital filter on each pin prevents pulses (Figure 4-58) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 4-57 and
Table 4-42).
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
t_ifmin
t_ifmax
Figure 4-57. Interrupt Glitch Filter on Port AD (PPS = 0)
Table 4-42. Pulse Detection Criteria
Pulse
STOP
Mode
STOP¹
Unit
Unit
Ignored
t_pulse <= 3
Bus Clock
t_pulse <= 3.2
µs
Uncertain
3 < t_pulse < 4
Bus Clock 3.2 < t_pulse < 10
µs
Valid
t_pulse >= 4
Bus Clock
t_pulse >= 10
µs
1 _{These values include the spread of the oscillator frequency over temperature,}
voltage and process.
MC9S12HZ256 Data Sheet, Rev. 2.04
164
Freescale Semiconductor