MC9S12HZ256 Datasheet, PDF (615/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 22 Module Mapping Control (MMCV4)
The HCS12 core architecture limits the physical address space available to 64K bytes. The program page
index register allows for integrating up to 1M byte of FLASH or ROM into the system by using the six
page index bits to page 16K byte blocks into the program page window located from 0x8000 to 0xBFFF
as defined in Table 22-14. CALL and RTC instructions have special access to read and write this register
without using the address bus.
NOTE
Normal writes to this register take one cycle to go into effect. Writes to this
register using the special access of the CALL and RTC instructions will be
complete before the end of the associated instruction.
Table 22-13. MEMSIZ0 Field Descriptions
Field
5:0
PIX[5:0]
Description
Program Page Index Bits 5:0 — These page index bits are used to select which of the 64 FLASH or ROM
array pages is to be accessed in the program page window as shown in Table 22-14.
PIX5
0
0
0
0
.
.
.
.
.
1
1
1
1
Table 22-14. Program Page Index Register Bits
PIX4
0
0
0
0
.
.
.
.
.
1
1
1
1
PIX3
0
0
0
0
.
.
.
.
1
1
1
1
PIX2
0
0
0
0
.
.
.
.
.
1
1
1
1
PIX1
0
0
1
1
.
.
.
.
.
0
0
1
1
PIX0
0
1
0
1
.
.
.
.
.
0
1
0
1
Program Space
Selected
16K page 0
16K page 1
16K page 2
16K page 3
.
.
.
.
.
16K page 60
16K page 61
16K page 62
16K page 63
22.4 Functional Description
The MMC sub-block performs four basic functions of the core operation: bus control, address decoding
and select signal generation, memory expansion, and security decoding for the system. Each aspect is
described in the following subsections.
22.4.1 Bus Control
The MMC controls the address bus and data buses that interface the core with the rest of the system. This
includes the multiplexing of the input data buses to the core onto the main CPU read data bus and control
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
615