MC9S12HZ256 Datasheet, PDF (25/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 1 MC9S12HZ256 Device Overview
1.2 Device Memory Map
Table 1-1 shows the device memory map for the MC9S12HZ256 out of reset.
Table 1-1. Device Register Map Overview
Address
Offset
0x0000–0x0017
0x0018–0x0019
0x001A–0x001B
0x001C–0x001F
0x0020–0x0027
0x0028–0x002F
0x0030–0x0033
0x0034–0x003F
0x0040–0x006F
0x0070–0x007F
0x0080–0x00AF
0x00B0–0x00BF
0x00C0–0x00C7
0x00C8–0x00CF
0x00D0–0x00D7
0x00D8–0x00DF
0x00E0–0x00FF
0x0100–0x010F
0x0110–0x011B
0x011C–0x011F
0x0120–0x0137
0x0140–0x017F
0x0180–0x01BF
0x01C0–0x01FF
0x0200–0x027F
0x0280–0x0287
0x0288–0x028F
0x0290–0x0297
0x0298–0x029F
0x02A0–0x02A7
0x02A8–0x03FF
Module
HCS12 Core (Ports A, B, E, Modes, Inits, Test)
Reserved
Device ID register (PARTID)
HCS12 Core (MEMSIZ, IRQ, HPRIO)
Reserved
HCS12 Core (Background Debug Mode)
HCS12 Core (PPAGE, Port K)
Clock and Reset Generator (PLL, RTI, COP)
Standard Timer Module 16-bit 8 channels (TIM)
Reserved
Analog-to-Digital Converter 10-bit 16 channels (ATD)
Reserved
Inter Integrated Circuit (IIC)
Serial Communications Interface 0 (SCI0)
Serial Communications Interface 1 (SCI1)
Serial Peripheral Interface (SPI)
Pulse Width Modulator 8-bit 6 channels (PWM)
Flash control registers
EEPROM control registers
Reserved
Liquid Crystal Display Driver 32x4 (LCD)
Scalable Controller Area Network 0 (MSCAN0)
Scalable Controller Area Network 1 (MSCAN1)
Motor Control Module (MC)
Port Integration Module (PIM)
Reserved
Stepper Stall Detector 0 (SSD0)
Stepper Stall Detector 1 (SSD1)
Stepper Stall Detector 2 (SSD2)
Stepper Stall Detector 3 (SSD3)
Reserved
Size
(Bytes)
24
2
2
4
8
8
4
12
48
16
48
16
8
8
8
8
32
16
12
4
24
64
64
64
128
8
8
8
8
8
344
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
25