MC9S12HZ256 Datasheet, PDF (129/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

4.3.1.8
Chapter 4 Port Integration Module (PIM9HZ256V2)
Port AD Interrupt Flag Register (PIFAD)
R
W
Reset
7
PIFAD7
0
6
PIFAD6
5
PIFAD5
4
PIFAD4
3
PIFAD3
2
PIFAD2
0
0
0
0
0
Figure 4-9. Port AD Interrupt Flag Register (PIFAD)
1
PIFAD1
0
0
PIFAD0
0
Read: Anytime. Write: Anytime.
Each flag is set by an active edge on the associated input pin. The active edge could be rising or falling
based on the state of the corresponding PPSADx bit. To clear each flag, write “1” to the corresponding
PIFADx bit. Writing a “0” has no effect.
NOTE
If the ATDDIEN1 bit of the associated pin is set to 0 (digital input buffer is
disabled), active edges can not be detected.
Table 4-8. PIFAD Field Descriptions
Field
Description
7:0
PIFAD[7:0]
Interrupt Flags Port AD
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a “1” clears the associated flag.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
129