MC9S12HZ256 Datasheet, PDF (143/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.5 Port S
Port S is associated with the serial peripheral interface (SPI) and serial communication interface (SCI0).
Each pin is assigned to these modules according to the following priority: SPI/SCI0 > general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the
SPI block description chapter for information on enabling and disabling the SPI.
When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and RXD0
respectively. Refer to the SCI block description chapter for information on enabling and disabling the SCI
receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
4.3.5.1 Port S I/O Register (PTS)
7
6
5
4
3
R
0
PTS7
PTS6
PTS5
PTS4
W
2
1
0
0
PTS1
PTS0
SPI/SCI:
SS
SCK
MOSI
MISO
TXD0
RXD0
Reset
0
0
0
0
0
0
0
0
= Reserved or Unimplemented
Figure 4-30. Port S I/O Register (PTS)
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled.
If enabled, the SCI0 transmitter takes precedence over the general-purpose I/O function, and the
corresponding TXD0 pin is configured as an output. If enabled, the SCI0 receiver takes precedence over
the general-purpose I/O function, and the corresponding RXD0 pin is configured as an input.
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
143