MC9S12HZ256 Datasheet, PDF (573/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 20 Interrupt (INTV1)
20.7 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request
by the CPU is shown in Table 20-5.
Table 20-5. Exception Vector Map and Priority
Vector Address
0xFFFE–0xFFFF
0xFFFC–0xFFFD
0xFFFA–0xFFFB
0xFFF8–0xFFF9
0xFFF6–0xFFF7
0xFFF4–0xFFF5
0xFFF2–0xFFF3
0xFFF0–0xFF00
Source
System reset
Crystal monitor reset
COP reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
XIRQ signal
IRQ signal
Device-specific I-bit maskable interrupt sources (priority in descending order)
MC9S12HZ256 Data Sheet, Rev. 2.04
Freescale Semiconductor
573