MC9S12HZ256 Datasheet, PDF (512/692 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 18 Background Debug Module (BDMV4)
18.3 Memory Map and Register Definition
A summary of the registers associated with the BDM is shown in Figure 18-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
18.3.1 Module Memory Map
Table 18-1. INT Memory Map
Register
Address
7
8–
Use
Reserved
BDM Status Register (BDMSTS)
Reserved
BDM CCR Holding Register (BDMCCR)
BDM Internal Register Position (BDMINR)
Reserved
Access
—
R/W
—
R/W
R
—
MC9S12HZ256 Data Sheet, Rev. 2.04
512
Freescale Semiconductor